During the mass-production of integrated circuits (IC), a supplementary electrostatic discharge (ESD) protection circuit is commonly placed between a power node (Vdd) and a ground node to prevent the core circuit from being attacked by an external electrostatic charge while not disrupting normal operation of the core circuit in regular working mode.
Refer to FIG. 1. FIG. 1 shows a conventional ESD protection circuit (also known as a clamping circuit). An ESD detecting unit 12, an ESD amplifying unit 14 and an ESD draining unit 16 are sitting between the power source and the ground.
When an ESD attacks (an ESD zap) said power node Vdd, the voltage level V1 between said ESD amplifying unit 14 and said detecting unit 12 instantly jumps to the same level as Vdd, causing said draining unit 16 to be activated and said power node Vdd to discharge through said draining unit 16. Said voltage level V1 gradually discharges through said detecting unit 12, ultimately changes the state of said ESD amplifying unit 14 and turns off said ESD draining unit 16.
Refer to FIG. 2. FIG. 2 shows another conventional ESD protection clamping circuit. For the purpose of the IC effectively discharging from Vdd when an ESD zap occurs without overly increasing the area of said detecting unit 12, a hysteresis unit (also known as a sustaining unit) 18 is implemented in said clamping circuit. Said sustaining unit 18 improves the discharging ability of said clamping circuit described below. When node V1 is attacked by an ESD zap and its voltage level is increased to the same as the power source Vdd, the voltage at the internal node V2 of said amplifying unit 14 is pulled to ground level, activating said sustaining unit 18 to form a closed current path from the power source Vdd to V1. At this moment, the current driving ability of said sustaining unit 18 on said node V1 is stronger than the discharging ability of said ESD detecting unit 12 on V1. As a result, the voltage level at V1 is maintained at the same level as said power source Vdd. By means of this positive feedback, when the IC encounters an ESD attack, said ESD draining unit 16 could continuously drain the ESD current from Vdd and therefore increases the protection provided by the clamping circuit on the core circuit in said IC.
On the other hand, the addition of said sustaining unit 18 also increases the risk of having a latch-up on said draining unit 16. For example, a sudden power on or a power bounce during normal operation can activate said clamping circuit. Once said clamping circuit is activated, a latch-up in said clamping circuit may occur since said sustaining unit is continuously on and so is said draining unit 16, drawing a significant amount of current from said power source Vdd to said ground.